The transistors in an integrated circuit have operating characteristics that vary with PVT variations. For example, the gate oxide might be fabricated thinner than specified and over etching of the gate polysilicon might produce a channel length shorter than specified. A CMOS inverter generally has increasing drive strength as its transistors have thinner gate oxides and shorter channels, as the power supply voltage increases, and as the operating temperature decreases. Thus, a combination of PVT variations might increase the drive strength of a CMOS inverter. Furthermore, certain PVT variations might affect the PMOS pull-up of a CMOS inverter differently than the NMOS pull-down of the CMOS inverter. Thus, certain PVT variations create a mismatch between the driving strength of the PMOS pull-up and the NMOS pull-down of the CMOS inverter. The mismatched driving strengths create a mismatch between the edge rates of the rising and falling transitions at the output signal of the CMOS inverter, and these mismatched transitions distort the duty cycle of the output signal. In addition, the allowable edge rates of the rising and falling transitions may be limited to prevent excitation of a high-frequency resonance at the output signal. However, it may be difficult to achieve the desired edge rates for both rising and falling transitions across the possible range of PVT variations, or an excessive limit on the edge rates might be required to meet the allowable edge rates across the possible range of PVT variations.
The internal circuitry of integrated circuits is powered by a power supply voltage that generally decreases as feature sizes become smaller in successive fabrication technologies. However, the signaling standards between integrated circuits continue to maintain backwards compatibility as feature sizes become smaller. A prevalent signaling standard has levels of 3.3 volts and zero volts. CMOS circuitry can provide this signaling standard from a 3.3 volt power supply because CMOS drives from rail-to-rail. This signaling standard is prevalent because it is backwards compatible with TTL logic levels powered from a 5 volt power supply. Thus, even though internal circuitry is powered with 1 volt or less in the current fabrication technologies, the signaling standards between integrated circuits continue to maintain backwards compatibility with an obsolete fabrication technology based on a 5 volt power supply.
The scaling of feature sizes in successive fabrication technologies includes progressively thinner gate oxides for the transistors. The thin gate oxide of current fabrication technologies cannot reliably withstand the 3.3 volts needed to drive the backwards compatible signaling standard. Thus, some fabrication technologies include a special thick gate oxide for fabricating transistors that reliably tolerate 3.3 volts. The internal circuitry is fabricated from transistors with the thin gate oxide, while the output drivers are fabricated from transistors with the special thick gate oxide.
There is a general need to drive output signals with legacy signaling standards. One or more embodiments may address one or more of the above issues.